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A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Hiroki FUJISAWA Takeshi SAKATA Tomonori SEKIGUCHI Kazuyoshi TORII Katsutaka KIMURA Kazuhiko KAJIGAYA
IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Nonvolatile Memories)
DRAM, ferroelectric memory, high speed, low-power, high-endurance,
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A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.