For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip
Shoji SHUKURI Kazumasa YANAGISAWA Koichiro ISHIBASHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: Flash Memories
ie-Flash, EPROM, fuse and redundancy,
Full Text: PDF(1005.6KB)>>
A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.