Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images

Wujian ZHANG  Runde ZHOU  Tsunehachi ISHITANI  Ryota KASAI  Toshio KONDO  

IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.3   pp.399-409
Publication Date: 2001/03/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
motion estimation,  low bit resolution,  VLSI architecture,  parallelism,  low power,  

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This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.