For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Cascade ALU Architecture for Asynchronous Super-Scalar Processors
Motokazu OZAWA Masashi IMAI Yoichiro UENO Hiroshi NAKAMURA Takashi NANYA
IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
asynchronous, superscalar processor, cascade ALU, fine grain pipeline,
Full Text: PDF>>
Wire delays, instead of gate delays, are moving into dominance in modern VLSI design. Current synchronous processors have the critical path not in the ALU function but in the cache access. Since the cache performance enhancement is limited by the memory access delay which mainly consists of wire delays, a reduction in gate delays may no longer imply any enhancement in processor performance. To solve this problem, this paper presents a novel architecture, called the Cascade ALU. The Cascade ALU allows super-scalar processors with future technologies to move the critical path into the ALU part. Therefore the Cascade ALU can enjoy the expected progress in future device speed. Since the delay of the Cascade ALU varies depending on the executed instructions, an asynchronous system is shown to be suitable for implementing the Cascade ALU. However an asynchronous system may have a large handshake overhead, this paper also presents an asynchronous Fine Grain Pipeline technique that hides the handshake overhead. Finally, this paper presents results of performance and area evaluation for an asynchronous implementation of the cascade ALU. The results show that the cascade ALU architecture has a good performance scalability on the reduction of the ALU latency and imposes little area penalty compared with current synchronous processors.