A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges

Koichiro MINAMI  Masayuki MIZUNO  Hiroshi YAMAGUCHI  Toshihiko NAKANO  Yusuke MATSUSHIMA  Yoshikazu SUMI  Takanori SATO  Hisashi YAMASHIDA  Masakazu YAMASHINA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.2   pp.220-228
Publication Date: 2001/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
delay-locked loop,  infinite phase capture ranges,  variable delay line,  dynamic phase detector,  

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Summary: 
This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.