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A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
Kazutoshi KOBAYASHI Makoto EGUCHI Takuya IWAHASHI Takehide SHIBAYAMA Xiang LI Kosuke TAKAI Hidetoshi ONODERA
Publication
IEICE TRANSACTIONS on Electronics
Vol.E84-C
No.2
pp.193-201 Publication Date: 2001/02/01 Online ISSN:
DOI: Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: VLSI, DSP, MSHVQ, videophone, video compression,
Full Text: PDF>>
Summary:
We propose a vector-pipeline processor VP-DSP for low-rate videophones which can encode and decode 10 frames/sec. of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 µm CMOS process. The area of the VP-DSP core is 4.26 mm2. It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W.
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