Fully Digital Preambleless 40 Mbps QPSK Receiver for Burst Transmission

Seung-Geun KIM  Wooncheol HWANG  Youngsun KIM  Youngkou LEE  Sungsoo CHOI  Kiseon KIM  

IEICE TRANSACTIONS on Electronics   Vol.E84-C    No.2    pp.175-182
Publication Date: 2001/02/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
QPSK receiver,  burst transmission,  timing recovery,  frequency offset recovery,  

Full Text: PDF>>
Buy this Article

We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.