A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor

Hiroshi OKANO  Atsuhiro SUGA  Hideo MIYAKE  Yoshimasa TAKEBE  Yasuki NAKAMURA  Hiromasa TAKAHASHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.2   pp.150-156
Publication Date: 2001/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLIW,  microprocessor,  multimedia,  SIMD,  synthesis,  

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Summary: 
A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm 7.5 mm. Since all circuit blocks were developed using logic synthesis, the processor is easy to adapt to system-on-a-chip (SoC) applications.