Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products

Kunio UCHIYAMA
Fumio ARAKAWA
Yasuhiko SAITO
Koki NOGUCHI
Atsushi HASEGAWA
Shinichi YOSHIOKA
Naohiko IRIE
Takeshi KITAHARA
Mark DEBBAGE
Andy STURGES

Publication
IEICE TRANSACTIONS on Electronics   Vol.E84-C    No.2    pp.139-149
Publication Date: 2001/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
embedded processor,  RISC,  SIMD,  system-on-chip,  multimedia,  

Full Text: PDF>>
Buy this Article



Summary: 
A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (6464b and 6432b), a split-branch mechanism, and virtual cache are also adopted in the architecture. A 714MIPS/9.6 GOPS/400 MHz processor core with the 64-bit architecture and a system LSI containing the core are developed using 0.15-µm technology. The LSI includes a 3.2 GB/sec high-bandwidth on-chip bus, a high-speed DRAM interface, a SRAM/Flash/ROM/Multiplexed-bus interface, and a 66 MHz PCI interface that provide the performance required for next-generation multimedia applications.