Fabrication Technology for Nb Integrated Circuits

Hideaki NUMATA  Shuichi TAHARA  

IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.1   pp.2-8
Publication Date: 2001/01/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Superconductive Electronics)
Category: Digital Applications
Nb,  Josephson junction,  etching,  planarization,  integration,  

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Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.