A New Concept of 3-Dimentional Multilayer-Stacked System-in-Package for Software-Defined-Radio

Kazuo TSUBOUCHI  Michio YOKOYAMA  Hiroyuki NAKASE  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.12   pp.1730-1734
Publication Date: 2001/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts)
Category: 
Keyword: 
system-in-package,  wireless communication,  flip-chip bump bonding,  3-D stacked package,  vertical bus line,  

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Summary: 
In the present GHz-clock high-density LSI, a design of signal lines is getting so critical that the transmission line analysis should be introduced to signal line design. This leads to the complex design of line structure and i/o drivers including impedance matching. Our target is to implement a system-in-package (SiP) for software-defined-radio (SDR). The SiP operates up to 10 GHz, and requires a compact and high-density packaging technology with a simple signal wiring design. In this paper, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5) 100-µm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines. A critical interconnect length, in which interconnect wiring is treated as a conventional RC line, is discussed for wiring design. Both wiring lengths in LSI chips and that among chips corresponding to total thickness of vertical bus lines are designed to be shorter than the critical length. The key points of the 3-D package for GHz signal transfer are a delay guarantee due to limitation of line length and separation between local lines in a chip and a bus line among chips.