Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer

Hiroshi TAKAHASHI  Masatsugu YAMADA  Yong-Gui XIE  Seiya KASAI  Hideki HASEGAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.10   pp.1344-1349
Publication Date: 2001/10/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
InP,  MISFET,  XPS,  C-V,  

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Summary: 
The fabrication process of a novel Si interface control layer (Si ICL)-based oxide-free insulated gate structure for InP metal-insulator-semiconductor field effect transistors (MISFETs) was successfully characterized and optimized using in-situ reflection of high-energy electron diffraction (RHEED), Raman scattering spectroscopy, X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques, and applied for fabrication of MISFETs. RHEED observation indicated that the optimum initial thickness of the Si ICL with single crystal pseudomorphic growth of Si on InP is 10 . Raman scattering spectroscopy showed existence of surface strain on InP covered with the Si ICL without changing LO-phonon peak width, indicating that the Si ICL is grown in a pseudomorphic fashion. A detailed XPS analysis showed that Fermi level pinning was largely reduced by the growth of the Si ICL and its partial electron cyclotron resonance (ECR) plasma nitridation realizing an optimum Si ICL thickness of 5 with a good interface to SiNx. C-V measurement confirmed that the optimum Si ICL-based gate formation process realized a full swing of Fermi level almost over the entire bandgap. The fabricated MISFET using the optimum gate structure exhibited excellent gate controllability and stable operation with a low gate leakage currents.