A Multimedia Architecture Extension for an Embedded RISC Processor

Ichiro KURODA  Kouhei NADEHARA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.9   pp.2255-2260
Publication Date: 2001/09/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
multimedia,  RISC microprocessor,  SIMD,  inverse discrete cosine transform,  

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This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.