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A Pipeline Chip for Quasi Arithmetic Coding
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/04/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
pipeline structure, compression, arithmetic coding, hardware-software combination,
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A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.