A Pipeline Chip for Quasi Arithmetic Coding

Yair WISEMAN  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A    No.4    pp.1034-1041
Publication Date: 2001/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
Keyword: 
pipeline structure,  compression,  arithmetic coding,  hardware-software combination,  

Full Text: PDF>>
Buy this Article



Summary: 
A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.