Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation

Shinsuke KOBAYASHI  Yoshinori TAKEUCHI  Akira KITAJIMA  Masaharu IMAI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.3   pp.748-754
Publication Date: 2001/03/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
multi-threading,  very long instruction word (VLIW),  instruction level parallelism,  thread level parallelism,  HW/SW co-design,  

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In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.