A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance

Tomohiro FUJITA  Hidetoshi ONODERA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.3   pp.727-734
Publication Date: 2001/03/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
analog LSI,  yield optimization,  hierarchical design,  constraint generation,  Mahalanobis' distance,  

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Summary: 
This paper presents a method of statistical system optimization. The method uses a constraint generation, which is a design methodology based on a hierarchical top-down design, to give specifications to sub-circuits of the system. The specifications are generated not only to reduce the costs of sub-circuits but also to take adequate margin to achieve enough yield of the system. In order to create an appropriate amount of margin, a term which expresses a statistical figure based on Mahalanobis' distance is added to the constraint generation problem. The method is applied to a PLL, and it is confirmed that the yield of the lock-up time reaches 100% after the optimization.