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A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers
Hyung Hoon KIM Kwang Sub YOON
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
multiplied folding amplifier, ADC, CMOS, current-mode, folding/interpolating,
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A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of 0.5LSB, an integral nonlinearity (INL) of 1.0LSB, 20 Ms/s of the data conversion rate, and the power dissipation of 180 mW with a power supply of 5 V.