A Low Offset 1.9-GHz Direct Conversion Receiver IC with Spurious Free Dynamic Range of over 67 dB

Shoji OTAKA  Takafumi YAMAJI  Ryuichi FUJIMOTO  Hiroshi TANIMOTO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.2   pp.513-519
Publication Date: 2001/02/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
direct conversion receiver,  double balanced mixer,  variable gain amplifier,  on-chip balun,  90 phase-shifter,  

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A direct conversion receiver IC including an on-chip balun, an I/Q mixer, a variable gain amplifier and a 90 phase-shifter is fabricated in a Bi-CMOS technology with 15 GHz transition frequency (fT). This paper demonstrates that cascaded connection of an on-chip balun and a double balanced mixer as the I/Q mixer is effective to achieve a low DC offset and a low second-order distortion, on the basis of both careful examination of the mixer behavior and measurement. Input-referred DC offset voltage of less than 300 µV and spurious free dynamic range (SFDR) of over 67 dB are obtained by measurement. The IC consumes 52 mA from 2.7 V power supply voltage. The die size is 3 mm 3 mm.