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Multibit Delta-Sigma Architectures with Two-Level Feedback Loop Using a Dual-Quantization Architecture
Noboru SAKIMURA Motoi YAMAGUCHI Michio YOTSUYANAGI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
A/D converter, delta-sigma modulator, noise-shaping, dual-quantization architecture,
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This paper proposes two novel Multi-bit Delta-Sigma Modulator (Δ Σ M) architectures based on a Dual-Quantization architecture. By using multi-bit quantization with single-bit feedback, Both eliminate the need for a multi-bit digital-to-analog converter (DAC) in the feedback loop. The first is a Digital quantization-Error Canceling Multi-bit (DECM)-Δ Σ M architecture that is able to achieve high resolution at a low oversampling ratio (OSR) because, by adjusting the coefficients of both analog and digital circuits, it is able to cancel completely the quantization error injected into the single-bit quantizer. Simulation results show that a signal-to-quantization-noise ratio of 90 dB is obtained with 3rd order 5-bit quantization DECM-Δ Σ M at an OSR of 32. The second architecture, an analog-to-digital mixed (ADM)-Δ Σ M architecture, uses digital integrators in place of the analog integrator circuits used in the Δ Σ M. This architecture reduces both die area and power dissipation. We estimate that a (2+2)-th order ADM-Δ Σ M with two analog-integrators and two digital-integrators will reduce the area of a 4-th order Δ Σ M by 15%.