A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board

Atsushi KAMO  Takayuki WATANABE  Hideki ASAI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.12   pp.3177-3181
Publication Date: 2001/12/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Circuit Theory
Krylov-subspace technique,  partial element equivalent circuit (PEEC),  network reduction,  decoupling capacitor,  

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This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.