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A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Design
PLL, phase adjust, variable delay, lock-up,
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Abstract-- Phase locked loop (PLL) is widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL.