For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time
Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
DFT strategies, full scan design methods, partial scan design methods, test point insertions, test application time,
Full Text: PDF(1.3MB)>>
As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.