Reducing Wire Lengths in the Layout of Cyclic Shifters

Peter-Michael SEIDEL  Mark A. HILLEBRAND  Thomas SCHURGER  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A    No.11    pp.2714-2721
Publication Date: 2001/11/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
cyclic shifter,  layout,  wire length,  wire delay,  

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Cyclic shifters are required in many central parts of microprocessors, floating-point units and DSPs. The main difficulty in conventional cyclic shifter designs are the long internal wire connections. For this reason we propose cyclic shifter layouts that improve the accumulated wire length on the critical path by rearranging the placement of the logical gates. We can show that in this way the wire length complexity on the critical path can be reduced from Ω(n log (n)) in conventional designs to O(n) in our optimized designs where n is the width of the shifted operand. For the practical case of n=64 we shorten the accumulated wire length on the critical path by a factor of 2.20. In the same design the maximal size of a net that has to be driven by a single gate is cut down by a factor of 1.86. This leads to faster cyclic shifter designs with lower power dissipation.