For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
floorplan, corner block list, simulated annealing, boundary constraints,
Full Text: PDF>>
Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.