An RTL Design-Space Exploration Method for High-Level Applications

Peng-Cheng KAO  Chih-Kuang HSIEH  Ching-Feng SU  Allen C.-H. WU  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A    No.11    pp.2648-2654
Publication Date: 2001/11/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword: 
design exploration,  high-level synthesis,  RTL,  design space,  AT-curve,  

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Summary: 
In this paper, we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performance-driven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration flow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.