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System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications
Chawalit HONSAWEK Kazuhito ITO Tomohiko OHTSUKA Trio ADIONO Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
system-MSPA, LSI design, videotelephony applications, H.263+ ITU standard,
Full Text: PDF(1MB)>>
In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176144 pixels) at the frame rate of 30 frame per second. The core size is 4.6 4.6 mm2 in a 0.35 µm process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand ability. Real time emulation and easy test capability with external PC is also implemented.