A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing

Sungkun LEE  Juho KIM  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.10   pp.2553-2560
Publication Date: 2001/10/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
buffer insertion,  transistor sizing,  optimization,  

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This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.