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An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults Tadayoshi HORITA Itsuo TAKANAMI Publication IEICE TRANSACTIONS on Information and Systems Vol.E83-D No.8 pp.1701-1705 Publication Date: 2000/08/25 Online ISSN: DOI: Print ISSN: 0916-8532 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: fault tolerant processor arrays, 1 1/2 track-switch model, self-reconfigurable system, run-time fault tolerance, wafer scale integration, Full Text: PDF(662.1KB)>>
Summary: We gave in [1] the software and hardware algorithms for reconfiguring 1 1/2-track switch 2-D mesh arrays with faults of processing elements, avoiding them. This paper shows an implementation of the hardware algorithm using an FPGA device, and by the logical simulation confirms the correctness of the behavior and evaluates reconfiguration time. From the result it is found that a self-repairable system is realizable and the system is useful for the run-time as well as fabrication-time reconfiguration because it requires no host computer to execute the reconfiguration algorithm and the reconfiguration time is very short. | ||||||||||
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