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Fast Testable Design for SRAM-Based FPGAs
Abderrahim DOUMAR Toshiaki OHMAMEUDA Hideo ITO
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerance
field programmable gate array (FPGA), testing, design for testing, shifting configurations,
Full Text: PDF(1.3MB)>>
This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.