For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data
Abderrahim DOUMAR Hideo ITO
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerance
defect tolerance, fault tolerance, field programmable gate array (FPGA), shifting configurations data, yield improvement,
Full Text: PDF(779.1KB)>>
The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and Horse-allocation) are introduced and compared.