For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Crossbar Arbiter Architecture for High-Speed MAPOS Switch
Tsuyoshi OGURA Satoru YAGI Tetsuo KAWANO Mitsuru MARUYAMA Naohisa TAKAHASHI
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Next Generation Internet Technologies and Their Applications)
MAPOS, high-speed switch, crossbar, arbiter,
Full Text: PDF(1.8MB)>>
This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulation-based performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware.