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Design of C-Testable Modified-Booth Multipliers
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerance
multiplier, modified Booth Algorithm, design for testability (DFT), C-testable design,
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In this paper, we consider the design for testability of a multiplier based on the modified Booth Algorithm. First, we present a basic array implementation of the multiplier. Next, we introduce testability considerations to derive two C-testable designs. The first of the designs is C-testable under the single stuck-at fault model (SAF) with 10 test patterns. And, the second is C-testable under the cell fault model (CFM) with 33 test patterns.