Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits

Ken-ichiro SONODA  Motoaki TANIZAWA  Kiyoshi ISHIKAWA  Norihiko KOTANI  Tadashi NISHIMURA  

IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.8   pp.1317-1323
Publication Date: 2000/08/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Circuit Applications
electrostatic discharge,  electrothermal simulation,  circuit simulation,  

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A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).