Interconnect Modeling in Deep-Submicron Design

Won-Young JUNG
Soo-Young OH
Jeong-Taek KONG
Keun-Ho LEE

IEICE TRANSACTIONS on Electronics   Vol.E83-C    No.8    pp.1311-1316
Publication Date: 2000/08/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Circuit Applications
statistical interconnect library generation,  interconnect modeling,  Monte Carlo method,  process variation,  

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As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.