Summary: In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.