Systematic Yield Simulation Methodology Applied to Fully-Depleted SOI MOSFET Process

Noriyuki MIURA  Hirokazu HAYASHI  Koichi FUKUDA  Kenji NISHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.8   pp.1288-1294
Publication Date: 2000/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Simulation Methodology and Environment
Keyword: 
fully-depleted SOI,  floating-body effect,  parasitic channel leakage,  systematic yield,  process optimization,  

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Summary: 
In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.