Comparison between Device Simulators for Gate Current Calculation in Ultra-Thin Gate Oxide n-MOSFETs

Eric CASSAN
Sylvie GALDIN
Philippe DOLLFUS
Patrice HESTO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C    No.8    pp.1194-1202
Publication Date: 2000/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Gate Tunneling Simulation
Keyword: 
MOSFETs,  downsizing,  gate oxide,  direct-tunneling,  hot carriers,  modeling,  

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Summary: 
The gate oxide of sub-0.1 µm MOSFETs channel length is expected to be reduced beyond 3 nm in spite of an increasing direct tunneling gate current. As tunnel injection modeling into SiO2 is expected to depend on the electron transport model adopted for the device description, a critical comparison is made in this paper between gate currents obtained from simulators based on Drift-Diffusion, Energy-Balance, and Monte Carlo models. The studied device is a 0.07 µm channel length n-MOSFET with 1.5 nm thick gate oxide. It is shown that positive drain voltage is responsible for two opposite effects on DT leakage: a carrier heating and a potential barrier hardening along the channel. It is proved by a careful study of Monte Carlo microscopic quantities that, contrary to what holds for thicker gate oxide transistors, the balance is favorable to the potential barrier effect. Injection into SiO2 is then dominated by near-thermal carriers injected at the channel beginning. For this reason, the gate current decreases when increasing the drain bias, with the maximum leakage obtained for (Vgs=Vdd, Vds=0), and a correct agreement is obtained between the Drift-Diffusion, Energy-Balance, and Monte Carlo approaches of gate current calculation, in spite of very different physical descriptions of transport at the microscopic level.