A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC

Tatsuji MATSUURA  Akihiro KITAGAWA  Toshiro TSUKADA  Eiki IMAIZUMI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.2   pp.227-235
Publication Date: 2000/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
low-power,  low-voltage,  cyclic A/D converter,  CMOS,  

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Summary: 
A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.