For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors
Kimio UEDA Koji NII Yoshiki WADA Shigenobu MAEDA Toshiaki IWAMATSU Yasuo YAMAGUCHI Takashi IPPOSHI Shigeto MAEGAWA Koichiro MASHIKO Yasutaka HORIBA
IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
SOI, CMOS, field-shield isolation, gate array, low-power, high-speed,
Full Text: PDF(2MB)>>
This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.