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System LSI Design Methods for Low Power LSIs
Hiroto YASUURA Tohru ISHIHARA
IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
low power design, system level, optimization, hardware/software codesign,
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Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.