A 1 V, 10.4 mW Low Power DSP Core for Mobile Wireless Use

Shoichiro KAWASHIMA
Tetsuyoshi SHIOTA
Isao FUKUSHI
Ryuhei SASAGAWA
Wataru SHIBAMOTO
Atsushi TSUCHIYA
Teruo ISHIHARA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C    No.11    pp.1739-1746
Publication Date: 2000/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
low-power,  MAC,  voltage up converter,  signal level converter,  1 V ROM,  

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Summary: 
An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.