Low-Power Area-Efficient Design of Embedded High-Speed A/D Converters

Daisuke MIYAZAKI  Shoji KAWAHITO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.11   pp.1724-1732
Publication Date: 2000/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
analog design method,  high-speed A/D converter,  low-power design,  

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Summary: 
In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.