A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size

Koji INOUE  Koji KAI  Kazuaki MURAKAMI  

IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.11   pp.1716-1723
Publication Date: 2000/11/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
cache,  low power,  variable line-size,  merged DRAM/logic LSIs,  high bandwidth,  

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This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.