The Effect of Impedance Loading Position on Induced Voltage Suppression

Hidetoshi YAMAMOTO  Shinichi SHINOHARA  Risaburo SATO  

Publication
IEICE TRANSACTIONS on Communications   Vol.E83-B    No.3    pp.569-576
Publication Date: 2000/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Recent Progress in Electromagnetic Compatibility Technology)
Category: EMC Design of PCB
Keyword: 
immunity,  suppression effect,  impedance,  induced voltage,  

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Summary: 
In this paper, the suppression of induced voltage on a printed wiring board through impedance loading by inserting impedance devices such as ferrite beads is focused on. How the suppression effect changes according to the insertion position of such devices is also investigated. Electromagnetic-field simulations were used to determine the distribution of voltage and current induced in wiring when a printed wiring board is exposed to an external electromagnetic field. Then, on the basis of these distributions, electromagnetic-field simulations were performed, and experiments were conducted to investigate the relationship between the insertion position of impedance devices and their suppression effect. It was verified that induced voltage can be large when a mismatch occurs between the impedance at the two ends of printed wiring, and that the suppression effect can differ significantly according to where an impedance device is inserted. A large effect was obtained by inserting an impedance device at a point 1/4 wavelength in distance from the end of a wire where voltage is being induced. In addition, comparing the use of resistors with the use of chip ferrite beads as impedance devices revealed similar tendencies in both. The above behavior was confirmed by numerical analysis.