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A Simple Phase Compensation Technique with Improved PSRR for CMOS Opamps
Tetsuro ITAKURA Tetsuya IIDA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
analog signal processing, integrated electronics, CMOS opamp, power supply rejection ratio, phase compensation,
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A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17 to 1.8 MHz and 44 for 200 pF load capacitance, respectively.