A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC

Byung-Woog CHO  Pyung CHOI  Jun-Rim CHOI  Dae-Hyuk KWON  Byung-Ki SOHN  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.6   pp.1192-1198
Publication Date: 2000/06/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Signal Processing
sigma-delta modulator,  analog-to-digital conversion,  gain scaling,  

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A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.