IEICE Trans - A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method

A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method

Jun-Young PARK  Jin-Ku KANG

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.6   pp.1100-1105
Publication Date: 2000/06/25
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category:
Keyword:
oversampling data recovery,  PLL,  DLL,  jitter,

Full Text: PDF>>

Summary:
This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.