PLL Frequency Synthesizer with Binary Phase Comparison

Shigeki OBOTE  Yasuaki SUMI  Naoki KITAI  Yutaka FUKUI  Yoshio ITOH  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.3   pp.427-434
Publication Date: 2000/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
PLL frequency synthesizer,  binary phase comparison,  

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Summary: 
In a phase-locked-loop (PLL) frequency synthesizer with binary phase comparison, jitter is hard to suppress. In this paper, we propose a PLL frequency synthesizer with an improved binary phase comparison which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.