Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider

Yasuaki SUMI  Shigeki OBOTE  Naoki KITAI  Hidekazu ISHII  Ryousuke FURUHASHI  Yutaka FUKUI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.3   pp.421-426
Publication Date: 2000/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
PLL frequency synthesizer,  prescaler,  multi-programmable divider,  (N+1/2) programmable divider,  

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Summary: 
In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.