A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm

Hyuk-Jun SUNG  Kwang Sub YOON  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.2   pp.267-271
Publication Date: 2000/02/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
dual-looped PLL,  PFD,  VCO,  V-I converter,  current-pumping algorithm,  

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This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.